Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a power-up signal generation circuit in a semiconductor integrated circuit.
A semiconductor integrated circuit (IC) includes an internal power supply voltage generation unit configured to stably operate various internal logic circuitry and other elements. The internal power supply voltage generation unit supplies internal power supply voltages to power terminals of the internal logic circuitry. When the internal power supply voltages have a proper voltage level during the application of an external power supply voltage, problems, such as latch-up, occur. In this case, it is difficult to guarantee the reliability of the semiconductor IC.
When the internal logic circuitry is not initialized to a specific value before power supply voltages are supplied to operate the elements thereof, a failure may occur due to a false data input and output during the operation of the IC. Therefore, a circuit to initialize the internal logic circuitry before the operation of the IC is required.
To prevent the latch up caused by the instability of the internal power supply voltage and to initialize the internal logic circuitry, the semiconductor IC includes a power-up signal generation circuit configured to generate a power-up signal.
FIG. 1 is a block diagram of a power-up signal generation circuit of a conventional semiconductor IC.
Referring to FIG. 1, the power-up signal generation circuit includes an external power supply voltage detection unit 110, an internal power supply voltage detection unit 120, and a combination unit 130. The external power supply voltage detection unit 110 is configured to detect a voltage level of an external power supply voltage VEXT and to generate a first power-up signal PUPB. The internal power supply voltage detection unit 120 is configured to detect a voltage level of an internal power supply voltage VINT and to generate a second power-up signal PUPBP. The combination unit 130 is configured to combine the first power-up signal PUPB and the second power-up signal PUPBP and to generate a final power-up signal PWRUP.
FIG. 2 is a waveform diagram of the power-up generation circuit of FIG. 1.
Referring to FIG. 2, power is externally supplied to increase the external power supply voltage VEXT. When the level of the external power supply voltage VEXT approaches a preset level, the external power supply voltage detection unit 110 detects the level such that the first power-up signal PUPB changes from a logic low level to a logic high level.
When the first power-up signal PUPB has changed to a logic high level, the internal power supply voltage generation unit is enabled to operate in response to the first power-up signal PUPB. Accordingly, the internal power supply voltage VINT increases.
When the internal power supply voltage increases to a stable level, the internal power supply voltage detection unit 120 detects the level such that the second power-up signal PUPBP changes from a logic low level to a logic high level.
The combination unit 130 changes the final power-up signal PWRUP from a logic low level to a logic high level in response to both the first and second power-up signals PUPB and PUPBP being changed from a logic low level to a logic high level. Therefore, when the final power-up signal PWRUP has changed from a logic low level to a logic high level, the internal logic circuitry of the semiconductor IC is activated.
FIG. 3 illustrates a circuit configuration of the internal power supply detection unit 120 of the conventional power-up signal generation circuit.
Referring to FIG. 3, the internal power supply detection unit 120 includes a block configured to lower a voltage of a detection node NC, a block configured to raise a voltage of the detection node NC, and a block configured to output the second power-up signal PUPBP in response to a voltage change of the detection node NC.
The block configured to lower a voltage of the detection node NC includes a PMOS transistor MP1, an NMOS transistor MN1, and a NMOS transistor MN2. The PMOS transistor MP1 has a source connected to the external power supply terminal VEXT and a drain connected to a node NA, and receives a ground voltage from a ground voltage terminal VSS through a gate thereof. The NMOS transistor MN1 has a source connected to the ground voltage terminal VSS and a drain and gate connected to the node NA. The NMOS transistor MN2 has a source connected to the ground voltage terminal VSS, a drain connected to the detection node NC, and a gate connected to the node NA.
The block configured to raise a voltage of the detection node NC includes a PMOS transistor MP2 and a PMOS transistor MP3. The PMOS transistor MP2 has a source connected to an internal power supply voltage terminal VINT and a drain and gate connected to a node NB. The PMOS transistor MP3 has a source connected to the node NB and a drain connected to the detection node NC, and receives a ground voltage from the ground voltage terminal VSS through a gate thereof.
The block configured to output the second power-up signal PUPBP in response to a voltage change of the detection node NC includes an inverter INV1, a PMOS transistor MP4, and an inverter INV2. The inverter INV1 has an input terminal connected to the detection node NC. The PMOS transistor MP4 has a source connected to the internal power supply voltage terminal VINT, a drain connected to the detection node NC, and a gate connected to an output node ND of the inverter INV1. The inverter INV2 has an input terminal connected to the output node ND, and outputs the second power-up signal PUPBP.
When the external power supply voltage VEXT is supplied in accordance with a power-up sequence, the voltage of the node NA increases to a threshold voltage Vth of the NMOS transistor MN1. Accordingly, the NMOS transistor MN2 is turned on to lower the voltage level of the detection node NC.
When the internal power supply voltage generation unit operates to increase the voltage level of the internal power supply voltage VINT, the PMOS transistor MP2 is turned on to increase the voltage level of the detection node NC. At this time, the discharge drive of the detection node NC by the NMOS transistor MN2 is continuously maintained. However, since the voltage level raising ability of the two PMOS transistors MP2 and MP3 is greater than the voltage level lowering ability of the NMOS transistor MN2, the voltage level of the detection node NC increases.
As such, when the level of the detection node NC increases to exceed a logic threshold value of the inverter INV1, the second power-up signal PUPBP changes to a logic high level. Since the node ND changes to a logic low level, the transistor MP4 is turned on to latch the detection node NC to a logic high level.
However, since the MOS transistor has a temperature characteristic, the threshold voltage decreases with a temperature increase (−2 mV/° C.). That is, at a high temperature, the threshold voltage decreases in comparison with the threshold voltage at a normal temperature. On the other hand, at a low temperature, the threshold voltage increases in comparison with a normal temperature.
Therefore, the threshold voltage Vth of the NMOS transistor NM1 increases in a low-temperature environment. This means that the voltage level of the node NA increases, and the voltage level lowering ability of the NMOS transistor NM2 for the detection node NC is improved by an increase of the gate voltage. On the other hand, since the threshold voltages Vth of the two PMOS transistors MP2 and MP3 also increase, the voltage level raising ability of the two PMOS transistors MP2 and MP3 for the detection node NC is reduced. In this case, the voltage of the detection node NC may not increase sufficiently. In a severe case, since the voltage of the detection node NC does not exceed the logic threshold value of the inverter INV1, the second power-up signal PUPBP does not change to a logic high level. When the second power-up signal PUPBP does not change to a logic high level, the final power-up signal PWRUP is not activated. Then, since the internal logic circuitry of the semiconductor IC is not initialized, a malfunction may occur.